CRC based hashing in FPGA using DSP blocks.
Tomás ZávodníkLukas KekelyViktor PusPublished in: DDECS (2014)
Keyphrases
- verilog hdl
- digital signal processing
- systolic array
- real time image processing
- signal processing
- digital signal
- high speed
- field programmable gate array
- hardware implementation
- data structure
- low power consumption
- data flow
- digital signal processors
- low power
- random projections
- nearest neighbor search
- block size
- binary codes
- digital signal processor
- hashing algorithm
- image processing
- low cost
- order preserving
- image blocks
- hash functions
- fpga implementation
- file organization
- variable size
- fractal image coding
- locality sensitive
- real time
- hardware design
- dedicated hardware
- hashing methods
- video copy detection
- fpga hardware
- power consumption