Using DSP blocks to compute CRC hash in FPGA (abstract only).
Viktor PusLukas KekelyTomás ZávodníkPublished in: FPGA (2014)
Keyphrases
- signal processing
- verilog hdl
- digital signal processing
- real time image processing
- systolic array
- high speed
- digital signal
- hardware implementation
- field programmable gate array
- digital signal processors
- learning algorithm
- low power consumption
- low level
- genetic algorithm
- higher level
- real time
- high level
- hardware design
- hashing algorithm
- computer vision
- image processing
- variable size
- parallel architecture
- block size
- computing systems
- low power
- b tree
- power consumption
- data acquisition
- data structure