Design methodology of configurable high performance packet parser for FPGA.
Viktor PusLukas KekelyJan KorenekPublished in: DDECS (2014)
Keyphrases
- design methodology
- hw sw
- low power consumption
- hardware software
- physical design
- low cost
- design criteria
- field programmable gate array
- design process
- design methodologies
- object oriented
- hardware implementation
- fuzzy neural network
- hardware design
- real time
- design procedure
- signal processing
- formal specification
- power consumption
- high speed
- database systems
- low power
- input output