Zdenek Kotásek

Publication Activity (10 Years)

Years Active: 1995-2021
Publications (10 Years): 45

Top Topics

Trained Neural Networks

Reliability Analysis

Functional Verification

Top Venues

Publications

Jakub Lojda, Richard Panek, Zdenek Kotásek
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. DSD (2021)
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD (2021)
Jakub Lojda, Richard Panek, Zdenek Kotásek
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. EWDTS (2021)
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS (2021)
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS (2020)
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD (2020)
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS (2020)
Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. LASCAS (2020)
Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS (2020)
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT (2020)
Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. DSD (2019)
Karel Szurman, Zdenek Kotásek
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. LATS (2019)
Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. LATS (2019)
Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. LATS (2019)
Martin Krcma, Zdenek Kotásek, Jakub Lojda
Detecting hard synapses faults in artificial neural networks. LATS (2019)
Karel Szurman, Zdenek Kotásek
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. DDECS (2019)
Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD (2019)
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD (2018)
Ondrej Cekan, Richard Panek, Zdenek Kotásek
Input and Output Generation for the Verification of ALU: A Use Case. EWDTS (2018)
Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD (2018)
Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. EWDTS (2018)
Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek
An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. EWDTS (2018)
Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
A Processor Optimization Framework for a Selected Application. EWDTS (2018)
Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS (2018)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Program Generation Through a Probabilistic Constrained Grammar. DSD (2018)
Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek
Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD (2017)
Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma
Data types and operations modifications: A practical approach to fault tolerance in HLS. EWDTS (2017)
Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek
Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. EWDTS (2017)
Martin Krcma, Zdenek Kotásek, Jakub Lojda
Triple modular redundancy used in field programmable neural networks. EWDTS (2017)
Ondrej Cekan, Zdenek Kotásek
A Probabilistic Context-Free Grammar Based Random Test Program Generation. DSD (2017)
Martin Krcma, Zdenek Kotásek, Jakub Lojda
Comparison of FPNNs models approximation capabilities and FPGA resources utilization. ICCP (2017)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek
Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems 52 (2017)
Martin Krcma, Zdenek Kotásek, Jakub Lojda
Implementation of fault tolerant techniques into FPNNs. FPT (2016)
Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek
HLS-based fault tolerance approach for SRAM-based FPGAs. FPT (2016)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD (2016)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT (2016)
Marcela Zachariásová, Michaela Kekelyova-Beleova, Zdenek Kotásek
Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis. DSD (2016)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Random stimuli generation based on a stochastic context-free grammar. FPT (2016)
Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. Microprocess. Microsystems 39 (8) (2015)
Martin Krcma, Zdenek Kotásek, Jan Kastil
Fault tolerant Field Programmable Neural Networks. NORCAS (2015)
Martin Krcma, Jan Kastil, Zdenek Kotásek
Mapping Trained Neural Networks to FPNNs. DDECS (2015)
Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek
FPGA Prototyping and Accelerated Verification of ASIPs. DDECS (2015)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Software Fault Tolerance: The Evaluation by Functional Verification. DSD (2015)
Michaela Beleova, Zdenek Kotásek, Marcela Simková, Toma Hruka
Application of Evolutionary Algorithms for Regression Suites Optimization. DDECS (2015)
Marcela Simková, Zdenek Kotásek
Automation and Optimization of Coverage-driven Verification. DSD (2015)
Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. DSD (2014)
Karel Szurman, Lukas Miculka, Zdenek Kotásek
State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. DSD (2014)
Lukas Miculka, Zdenek Kotásek
Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA. DDECS (2014)
Lucie Matuova, Jan Kastil, Zdenek Kotásek
Automatic Construction of On-line Checking Circuits Based on Finite Automata. DSD (2014)
Lukas Miculka, Martin Straka, Zdenek Kotásek
Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. DSD (2013)
Marcela Simková, Zdenek Prikryl, Zdenek Kotásek, Tomas Hruska
Automated Functional Verification of Application Specific Instruction-set Processors. IESS (2013)
Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek
Fault tolerant CAN bus control system implemented into FPGA. DDECS (2013)
Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka
Fault tolerant system design and SEU injection based testing. Microprocess. Microsystems 37 (2) (2013)
Marcela Simková, Zdenek Kotásek, Cristiana Bolchini
Analysis and comparison of functional verification and ATPG for testing design reliability. DDECS (2013)
Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD (2012)
Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná
pecial CAI Section Devoted to MEMICS '11: Preface. Comput. Informatics 31 (3) (2012)
Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek
Test platform for fault tolerant systems design properties verification. DDECS (2012)
Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek
Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS (2011)
Martin Straka, Jan Kastil, Zdenek Kotásek
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD (2011)
Pavel Bartos, Zdenek Kotásek, Jan Dohnal
Decreasing test time by scan chain reorganization. DDECS (2011)
Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES (2010)
Martin Straka, Jan Kastil, Zdenek Kotásek
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS (2010)
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS (2010)
Martin Straka, Jan Kastil, Zdenek Kotásek
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD (2010)
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD (2010)
Martin Straka, Zdenek Kotásek
High Availability Fault Tolerant Architectures Implemented into FPGAs. DSD (2009)
Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar
Preface. Electron. Notes Theor. Comput. Sci. 251 (2009)
Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman
Power Conscious RTL Test Scheduling. DSD (2008)
Martin Straka, Zdenek Kotásek, Jan Winter
Digital Systems Architectures Based on On-line Checkers. DSD (2008)
Josef Strnadel, Tomas Pecenka, Zdenek Kotásek
Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Comput. Informatics 27 (6) (2008)
Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman
Testability analysis based on the identification of testable blocks with predefined properties. Microprocess. Microsystems 32 (5-6) (2008)
Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda
Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. 4 (2) (2008)
Lukás Starecek, Lukás Sekanina, Zdenek Kotásek
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS (2008)
Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek
Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13 (3) (2008)
Martin Straka, Jiri Tobola, Zdenek Kotásek
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT (2007)
Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD (2007)
Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka
Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD (2007)
Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS (2006)
Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS (2006)
Josef Strnadel, Zdenek Kotásek
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS (2006)
Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS (2006)
Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
Testability Estimation Based on Controllability and Observability Parameters. DSD (2006)
Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware (2005)
Josef Strnadel, Zdenek Kotásek
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD (2005)
Daniel Mika, Josef Strnadel, Zdenek Kotásek
The Identification of registers in RTL Structures for the Test Application. ISoLA (Preliminary proceedings) (2004)
Zdenek Kotásek, Daniel Mika, Josef Strnadel
Test scheduling for embedded systems. DSD (2003)
Josef Strnadel, Zdenek Kotásek
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD (2002)
Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka
Formal Approach to the RTL Testability Analysis. LATW (2000)
Zdenek Kotásek, F. Zboril
RT level testability analysis to reduce test application time. EUROMICRO (1997)
J. Blatný, Zdenek Kotásek, Jan Hlavicka
RT Level Test Scheduling. Comput. Artif. Intell. 16 (1) (1997)
J. Blatný, Zdenek Kotásek
I-Path Analysis. Comput. Artif. Intell. 14 (5) (1995)