Lukás Starecek

Publication Activity (10 Years)

Years Active: 2006-2010
Publications (10 Years): 0

Publications

Jirí Simácek, Lukás Sekanina, Lukás Starecek
Evolutionary Design of Reconfiguration Strategies to Reduce the Test Application Time. ICES (2010)
Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda
Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. 4 (2) (2008)
Lukás Starecek, Lukás Sekanina, Zdenek Kotásek
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS (2008)
Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS (2006)
Lukás Sekanina, Lukás Starecek, Zdenek Kotásek
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS (2006)