Ondrej Cekan

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 22

Top Topics

Fault Tolerance

Central Pattern Generator

Top Venues

Publications

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS (2021)
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS (2020)
Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD (2020)
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS (2020)
Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. LASCAS (2020)
Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS (2020)
Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. DSD (2019)
Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD (2019)
Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD (2018)
Ondrej Cekan, Richard Panek, Zdenek Kotásek
Input and Output Generation for the Verification of ALU: A Use Case. EWDTS (2018)
Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD (2018)
Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek
A Processor Optimization Framework for a Selected Application. EWDTS (2018)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Program Generation Through a Probabilistic Constrained Grammar. DSD (2018)
Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek
Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD (2017)
Ondrej Cekan, Zdenek Kotásek
A Probabilistic Context-Free Grammar Based Random Test Program Generation. DSD (2017)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek
Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems 52 (2017)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD (2016)
Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT (2016)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Random stimuli generation based on a stochastic context-free grammar. FPT (2016)
Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. Microprocess. Microsystems 39 (8) (2015)
Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek
FPGA Prototyping and Accelerated Verification of ASIPs. DDECS (2015)
Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek
Software Fault Tolerance: The Evaluation by Functional Verification. DSD (2015)
Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. DSD (2014)