Input and Output Generation for the Verification of ALU: A Use Case.

Ondrej Cekan Richard Panek Zdenek Kotásek

Published in: EWDTS (2018)

Keyphrases

desired output
input data
multiple output
input variables
model checking
floating point
feedback loop
input patterns
input vector
data model
face verification
signature verification
hidden units
asynchronous circuits
output space
multiple input