Josef Strnadel

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 9

Top Topics

Temporal Properties

Reactive Systems

Top Venues

Comput. Informatics

Publications

Josef Strnadel
Analyzing Dynamic Aspects of AxC Systems by Means of Statistical Model Checking. DDECS (2022)
Josef Strnadel
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. DDECS (2021)
Josef Strnadel
Statistical Model Checking of Approximate Circuits: Challenges and Opportunities. DATE (2020)
Josef Strnadel
Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates. DATE (2019)
Josef Strnadel
Predictability Analysis of Interruptible Systems by Statistical Model Checking. IEEE Des. Test 35 (2) (2018)
Josef Strnadel
Statistical Model Checking of Processor Systems in Various Interrupt Scenarios. ISoLA (2) (2018)
Josef Strnadel
On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking. DSD (2017)
Josef Strnadel
On Creation and Analysis of Reliability Models by Means of Stochastic Timed Automata and Statistical Model Checking: Principle. ISoLA (1) (2016)
Josef Strnadel
Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads. ECBS-EERC (2015)
Josef Strnadel, Martin Pokorny
Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework. DSD (2014)
Josef Strnadel, Frantisek Slimarik
Impact of Software Fault Tolerance to Fault Effects in OS-Driven RT Systems. Comput. Informatics 33 (4) (2014)
Josef Strnadel
On design of priority-driven load-adaptive monitoring-based hardware for managing interrupts in embedded event-triggered real-time systems. DDECS (2013)
Josef Strnadel
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates. ARCS (2013)
Josef Strnadel
Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems. DDECS (2012)
Josef Strnadel, Frantisek Slimarik
On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels. DSD (2012)
Michal Rumplík, Josef Strnadel
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits. DSD (2011)
Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES (2010)
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS (2010)
Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD (2010)
Josef Strnadel
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. DSD (2008)
Josef Strnadel, Tomas Pecenka, Zdenek Kotásek
Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Comput. Informatics 27 (6) (2008)
Richard Ruzicka, Josef Strnadel
Test Controller Synthesis Constrained by Circuit Testability Analysis. DSD (2007)
Josef Strnadel, Arghya Kumar Dhali
Novel Optimizing Approach in the Area of STEP-Based Construction of Sessionless, Power-Constrainted, TAM and Time Optimal Test Schedules. ECBS (2006)
Josef Strnadel, Zdenek Kotásek
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS (2006)
Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina
Testability Estimation Based on Controllability and Observability Parameters. DSD (2006)
Josef Strnadel
Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Comput. Artif. Intell. 25 (5) (2006)
Josef Strnadel
Power-Constrained, Sessionless SoC Test Scheduling Based on Exploration of I-Schedule State-Space. DDECS (2006)
Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware (2005)
Josef Strnadel, Zdenek Kotásek
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD (2005)
Daniel Mika, Josef Strnadel, Zdenek Kotásek
The Identification of registers in RTL Structures for the Test Application. ISoLA (Preliminary proceedings) (2004)
Zdenek Kotásek, Daniel Mika, Josef Strnadel
Test scheduling for embedded systems. DSD (2003)
Josef Strnadel, Zdenek Kotásek
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD (2002)