Statistical Model Checking of Processor Systems in Various Interrupt Scenarios.
Josef StrnadelPublished in: ISoLA (2) (2018)
Keyphrases
- model checking
- temporal logic
- automated verification
- finite state machines
- formal methods
- formal verification
- finite state
- model checker
- reactive systems
- asynchronous circuits
- artifact centric
- temporal properties
- process algebra
- verification method
- symbolic model checking
- concurrent systems
- transition systems
- formal specification
- pspace complete
- bounded model checking
- reachability analysis
- distributed systems
- artificial intelligence