Advanced fault tolerant bus for multicore system implemented in FPGA.

Martin Straka Jan Kastil Jaroslav Novotný Zdenek Kotásek

Published in: DDECS (2011)

Keyphrases

fault tolerant
fault tolerance
distributed systems
high speed
high availability
load balancing
artificial intelligence
evolvable hardware
safety critical
low cost
reconfigurable hardware
pipelined architecture
field programmable gate array
data structure
real time
mobile agent system
fpga hardware