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General memory efficient packet matching FPGA architecture for future high-speed networks.

Michal KekelyLukás KekelyJan Korenek
Published in: Microprocess. Microsystems (2020)
Keyphrases
  • memory efficient
  • high speed networks
  • high speed
  • real time
  • management system
  • hardware implementation
  • packet loss
  • network conditions
  • computational complexity
  • distributed database systems