Arindam Banerjee

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 5

Top Topics

Top Venues

IET Comput. Digit. Tech.

Publications

Arindam Banerjee, Debesh Kumar Das
A Novel ALU Circuit based on Reversible Logic. J. Circuits Syst. Comput. 29 (11) (2020)
Arindam Banerjee, Debesh Kumar Das
Arithmetic Circuits Using Reversible Logic: A Survey Report. ACSS (1) (2019)
Arindam Banerjee, Debesh Kumar Das
A new ALU architecture design using reversible logic. ISED (2016)
Arindam Banerjee, Debesh Kumar Das
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. VLSI Design (2016)
Arindam Banerjee, Debesh Kumar Das
A New Squarer design with reduced area and delay. IET Comput. Digit. Tech. 10 (5) (2016)
Arindam Banerjee, Debesh Kumar Das
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. J. Low Power Electron. 11 (4) (2015)
Arindam Banerjee, Debesh Kumar Das
Squarer design with reduced area and delay. VDAT (2015)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8 (1) (2014)
Arindam Banerjee, Debesh Kumar Das
Squaring in reversible logic using iterative structure. EWDTS (2014)
Arindam Banerjee, Debesh Kumar Das
The Design of Reversible Multiplier Using Ancient Indian Mathematics. ISED (2013)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT (2012)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42 (12) (2011)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED (2011)