Prabir Saha

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 9

Top Topics

Underlying Assumptions

Power Dissipation

Top Venues

J. Circuits Syst. Comput.

Period. Polytech. Electr. Eng. Comput. Sci.

IET Circuits Devices Syst.

Publications

Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication. Integr. 94 (2024)
Srikant Kumar Beura, Bishnulatpam Pushpa Devi, Prabir Saha, Pramod Kumar Meher
Design of a Novel Inexact 4:2 Compressor and Its Placement in the Partial Product Array for Area, Delay, and Power-Efficient Approximate Multipliers. Circuits Syst. Signal Process. 43 (6) (2024)
Sheba Diamond Thabah, Prabir Saha
Minimizing Ancilla Inputs and Garbage Outputs of Reversible BCD Multiplier. J. Circuits Syst. Comput. 31 (4) (2022)
Srikant Kumar Beura, Gudmalwar Ashishkumar Prabhakar, Sudesna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha
Design and Analysis of Inexact 3: 2 Compressor-based Radix-4 Multiplier towards Image Multiplication. ICCCNT (2021)
Sheba Diamond Thabah, Prabir Saha
Improved Signed Binary Multiplier Through New Partial Product Generation Scheme. J. Circuits Syst. Comput. 30 (9) (2021)
Sheba Diamond Thabah, Prabir Saha
New design approaches of reversible BCD encoder using Peres and Feynman gates. ICT Express 6 (1) (2020)
Rekib Uddin Ahmed, Prabir Saha
Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation. Period. Polytech. Electr. Eng. Comput. Sci. 64 (2020)
Sheba Diamond Thabah, Prabir Saha
A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder. Period. Polytech. Electr. Eng. Comput. Sci. 64 (4) (2020)
Rekib Uddin Ahmed, Prabir Saha
Modeling of Threshold Voltage and Subthreshold Current for P-Channel Symmetric Double-Gate MOSFET in Nanoscale Regime. iNIS (2017)
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
Design of 64-Bit Squarer Based on Vedic Mathematics. J. Circuits Syst. Comput. 23 (7) (2014)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8 (1) (2014)
Prabir Saha, Deepak Kumar, P. Bhattacharyya, Anup Dandapat
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. ISED (2013)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT (2012)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42 (12) (2011)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED (2011)