Anup Dandapat

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 20

Top Topics

Power Dissipation

Associative Memory

Design Methodology

Content Addressable Memory

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

J. Circuits Syst. Comput.

Publications

Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine. Integr. 98 (2024)
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
SMS-CAM: Shared matchline scheme for content addressable memory. Integr. 88 (2023)
Keshab Das, Anup Dandapat, Sanjay Kumar Jana
Design of a 1.29-1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation. J. Circuits Syst. Comput. 31 (16) (2022)
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
Match-line control unit for power and delay reduction in hybrid CAM. IET Circuits Devices Syst. 15 (3) (2021)
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM). J. Inf. Sci. Eng. 36 (5) (2020)
Sandeep Mishra, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Anup Dandapat
The analogy of matchline sensing techniques for content addressable memory (CAM). IET Comput. Digit. Tech. 14 (3) (2020)
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
Low-power content addressable memory design using two-layer P-N match-line control and sensing. Integr. 75 (2020)
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2020)
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
Low discharge precharge free matchline structure for energy-efficient search using CAM. Integr. 69 (2019)
Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Sandeep Mishra, Anup Dandapat
A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory. iSES (2019)
Sandeep Mishra, Telajala Venkata Mahendra, Jyotishman Saikia, Anup Dandapat
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2018)
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory. IEEE Trans. Consumer Electron. 64 (3) (2018)
Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. VLSI Design (2017)
Sandeep Mishra, Anup Dandapat
Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage. IEEE Trans. Circuits Syst. II Express Briefs (6) (2017)
Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Vinay Kumar, Anup Dandapat
Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique. J. Circuits Syst. Comput. 25 (12) (2016)
Sandeep Mishra, Anup Dandapat
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Vinay Kumar, Chandan Kumar Jha, Gaurav Thapa, Anup Dandapat
A Novel Methodology for Design of Cyclic Combinational Circuits. J. Low Power Electron. 12 (3) (2016)
Sandeep Mishra, Telajala Venkata Mahendra, Anup Dandapat
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
Design of 64-Bit Squarer Based on Vedic Mathematics. J. Circuits Syst. Comput. 23 (7) (2014)
D. Kayal, Posiba Mostafa, Anup Dandapat, Chandan Kumar Sarkar
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique. J. Signal Process. Syst. 76 (1) (2014)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8 (1) (2014)
Prabir Saha, Deepak Kumar, P. Bhattacharyya, Anup Dandapat
Reciprocal Unit Based on Vedic Mathematics for Signal Processing Applications. ISED (2013)
D. Ghosh, P. C. Mondal, D. Kayal, P. Bhattacharyya, Anup Dandapat
A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique. J. Low Power Electron. 9 (4) (2013)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT (2012)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42 (12) (2011)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED (2011)
Anup Dandapat, D. Kayal, D. Mukhopadhyay
Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM. J. Low Power Electron. 4 (2) (2008)