Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit.
Partha BhattacharyyaBijoy KunduSovan GhoshVinay KumarAnup DandapatPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
- low power
- high speed
- logic circuits
- power dissipation
- shift register
- power consumption
- high power
- low cost
- wireless transmission
- cmos technology
- single chip
- real time
- gate array
- digital signal processing
- power reduction
- vlsi circuits
- bit parallel
- nm technology
- image sensor
- vlsi architecture
- low power consumption
- frame rate
- data flow
- mixed signal
- delay insensitive