Partha Bhattacharyya

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 4

Top Topics

Hybrid Approaches

Automatic Analysis

Top Venues

IEEE Trans. Instrum. Meas.

IET Circuits Devices Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Indranil Maity, Hafizur Rahaman, Partha Bhattacharyya
DFT Based Simulation for Predicting Alcohol Adsorption on Oxygenated Functional Group Containing GO and rGO Based Gas Sensor Devices. ISDCS (2020)
Sanghamitra Ghosal, Indranil Maity, Partha Bhattacharyya
NT/RGO Hybrid Sensing Layer with embedded Micro hot Plate. ISDCS (2019)
Indranil Maity, Partha Bhattacharyya
Potentiallity of Surface Modified TiO2 Nanoflowers for Alcohol Sensing Application. ISDCS (2019)
Debanjan Acharyya, Rajarshi Roy Chaudhuri, Partha Bhattacharyya
Noise Analysis-Resonant Frequency-Based Combined Approach for Concomitant Detection of Unknown Vapor Type and Concentration. IEEE Trans. Instrum. Meas. 68 (8) (2019)
Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar, Anup Dandapat
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Prabir Saha, Deepak Kumar, Partha Bhattacharyya, Anup Dandapat
Design of 64-Bit Squarer Based on Vedic Mathematics. J. Circuits Syst. Comput. 23 (7) (2014)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Improved matrix multiplier design for high-speed digital signal processing applications. IET Circuits Devices Syst. 8 (1) (2014)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
Design of High Speed Vedic Multiplier for Decimal Number System. VDAT (2012)
Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya
ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics. Microelectron. J. 42 (12) (2011)
Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat
Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications. ISED (2011)