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A Novel Low-Power Matchline Evaluation Technique for Content Addressable Memory (CAM).
Telajala Venkata Mahendra
Sheikh Wasmir Hussain
Sandeep Mishra
Anup Dandapat
Published in:
J. Inf. Sci. Eng. (2020)
Keyphrases
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low power
content addressable memory
high speed
low cost
power consumption
high power
single chip
low power consumption
vlsi circuits
logic circuits
vlsi architecture
real time