Chandan Kumar Sarkar

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 22

Top Topics

Integer Arithmetic

Field Effect Transistors

Top Venues

IET Circuits Devices Syst.

Microelectron. Reliab.

J. Low Power Electron.

Publications

Angsuman Sarkar, Chandan Kumar Sarkar, Arezki Benfdila
Introduction to the special section on State-of-the-art Micro-Nano devices and systems. Comput. Electr. Eng. 100 (2022)
Avtar Singh, Saurabh Chaudhury, Manash Chanda, Chandan Kumar Sarkar
Split gated silicon nanotube FET for bio-sensing applications. IET Circuits Devices Syst. 14 (8) (2020)
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures. Microelectron. J. 90 (2019)
Avtar Singh, Saurabh Chaudhury, Chandan Kumar Pandey, Savitesh Madhulika Sharma, Chandan Kumar Sarkar
silicon nanotube tunnel FET device. IET Circuits Devices Syst. 13 (8) (2019)
Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application. IET Circuits Devices Syst. 13 (3) (2019)
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET. IEEE Trans. Circuits Syst. II Express Briefs (7) (2018)
Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing. IET Circuits Devices Syst. 12 (4) (2018)
Swapan Das, Chandan Kumar Sarkar, Sunipa Roy
Development of integrated microsystem for hydrogen gas detection. IET Circuits Devices Syst. 12 (4) (2018)
Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar
Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs. IET Circuits Devices Syst. 11 (1) (2017)
Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application. J. Low Power Electron. 13 (3) (2017)
Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance. IET Circuits Devices Syst. 10 (6) (2016)
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
Study of process induced variability of germanium-pTFET in analog and RF domain. Microelectron. Reliab. 65 (2016)
Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET. ACM J. Emerg. Technol. Comput. Syst. 12 (4) (2016)
Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan Kumar Sarkar
Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET. Microelectron. Reliab. 61 (2016)
Sagar Mukherjee, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor. IET Circuits Devices Syst. 10 (3) (2016)
Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar
Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs. Microelectron. Reliab. 61 (2016)
Atanu Kundu, Arka Dutta, Chandan Kumar Sarkar
Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications. J. Low Power Electron. 11 (4) (2015)
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET. Microelectron. J. 46 (11) (2015)
Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar
Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs. J. Low Power Electron. 11 (3) (2015)
Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Sayani Ghosh, Kalyan Koley, Chandan Kumar Sarkar
Impact of the lateral straggle on the Analog and RF performance of TFET. Microelectron. Reliab. 55 (2) (2015)
Manash Chanda, Swapnadip De, Chandan Kumar Sarkar
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application. J. Circuits Syst. Comput. 24 (10) (2015)
Sudhansu Kumar Pati, Kalyan Koley, Arka Dutta, N. Mohankumar, Chandan Kumar Sarkar
Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs. Microelectron. Reliab. 54 (6-7) (2014)
Atanu Kundu, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET. Microelectron. Reliab. 54 (12) (2014)
Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar
Analysis of flicker and thermal noise in p-channel Underlap DG FinFET. Microelectron. Reliab. 54 (8) (2014)
D. Kayal, Posiba Mostafa, Anup Dandapat, Chandan Kumar Sarkar
Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique. J. Signal Process. Syst. 76 (1) (2014)
Arka Dutta, Kalyan Koley, Chandan Kumar Sarkar
Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer. Microelectron. Reliab. 54 (6-7) (2014)
Atanu Kundu, Arka Dutta, Kalyan Koley, S. Niyogi, Chandan Kumar Sarkar
RF parameter extraction of underlap DG MOSFETs: a look up table based approach. IET Circuits Devices Syst. 8 (6) (2014)
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. CoRR (2013)
P. Bhattacharyya, Sunipa Roy, Chandan Kumar Sarkar
Integration of ZnO nanoflakes with MEMS platform and its application as gas sensor. ICST (2013)
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. CoRR (2013)
Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit. VDAT (2012)
Angsuman Sarkar, Aloke Kumar Das, Swapnadip De, Chandan Kumar Sarkar
Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron. J. 43 (11) (2012)
Angsuman Sarkar, Swapnadip De, Anup Dey, Chandan Kumar Sarkar
1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model. IET Circuits Devices Syst. 6 (1) (2012)
Srabanti Pandit, Binit Syamal, Chandan Kumar Sarkar
Modeling of noise for p-channel DG-FinFETs. Microelectron. Reliab. 52 (6) (2012)
Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. ISED (2012)
Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ISED (2012)
Kalyan Koley, Binit Syamal, Atanu Kundu, N. Mohankumar, Chandan Kumar Sarkar
Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions. Microelectron. Reliab. 52 (11) (2012)
A. Srivastava, R. K. Nahar, Chandan Kumar Sarkar, W. P. Singh, Y. Malhotra
Study of hafnium oxide deposited using Dense Plasma Focus machine for film structure and electrical properties as a MOS device. Microelectron. Reliab. 51 (4) (2011)
D. Zade, Soshi Sato, Kuniyuki Kakushima, A. Srivastava, Parhat Ahmet, Kazuo Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji Natori, Takeo Hattori, Chandan Kumar Sarkar, Hiroshi Iwai
gated nMOSFETs on low-frequency noise. Microelectron. Reliab. 51 (4) (2011)
Saurav Chakraborty, Abhijit Mallik, Chandan Kumar Sarkar
Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications. IET Circuits Devices Syst. 5 (4) (2011)
Srabanti Pandit, Chandan Kumar Sarkar
Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs. VLSI Design (2011)
A. Chakraborty, Chandan Kumar Sarkar
N/GaN at microwave frequencies. Microelectron. Reliab. 50 (7) (2010)
Debdatta Kandar, Sourav Dhar, Rabindranath Bera, Chandan Kumar Sarkar
MIMO Based Multimedia Communication System CoRR (2009)
A. Srivastava, Partha Sarkar, Chandan Kumar Sarkar
Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications. Microelectron. Reliab. 49 (4) (2009)
N. Mohankumar, Binit Syamal, Chandan Kumar Sarkar
Investigation of novel attributes of single halo dual-material double gate MOSFETs for analog/RF applications. Microelectron. Reliab. 49 (12) (2009)
Partha Sarkar, Abhijit Mallik, Chandan Kumar Sarkar
Study on the performance of sub 100 nm LACLATI MOSFETs for digital application. Microelectron. Reliab. 49 (4) (2009)
Srimanta Baishya, Abhijit Mallik, Chandan Kumar Sarkar
A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain. Microelectron. Reliab. 48 (1) (2008)
M. Ganguly, Chandan Kumar Sarkar
Realization of quantum dot Boolean logic gate for image processing applications. J. Electronic Imaging 16 (2) (2007)
Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar
Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. VLSI-SoC (2007)
Partha Sarkar, Abhijit Mallik, Chandan Kumar Sarkar
Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs. Microelectron. Reliab. 47 (6) (2007)
S. Shrestha, Chandan Kumar Sarkar
As/InP systems at low temperatures. Microelectron. J. 37 (8) (2006)