Sagar Mukherjee

Publication Activity (10 Years)

Years Active: 2012-2019
Publications (10 Years): 4

Top Topics

Functional Decomposition

Top Venues

IET Circuits Devices Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Swarnil Roy, Sagar Mukherjee, Arka Dutta, Chandan Kumar Sarkar, Chayanika Bose
Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application. IET Circuits Devices Syst. 13 (3) (2019)
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Chandan Kumar Sarkar
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET. IEEE Trans. Circuits Syst. II Express Briefs (7) (2018)
Sagar Mukherjee, Swarnil Roy, Arka Dutta, Chandan Kumar Sarkar
Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance. IET Circuits Devices Syst. 10 (6) (2016)
Sagar Mukherjee, Kalyan Koley, Arka Dutta, Chandan Kumar Sarkar
Low-power amplitude modulator for wireless application using underlap double-gate metal-oxide-semiconductor field-effect transistor. IET Circuits Devices Syst. 10 (3) (2016)
Sagar Mukherjee, Arka Dutta, Swarnil Roy, Kalyan Koley, Chandan Kumar Sarkar
Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET. Microelectron. J. 46 (11) (2015)
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. CoRR (2013)
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. CoRR (2013)
Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. ISED (2012)
Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ISED (2012)