Subhramita Basak

Publication Activity (10 Years)

Years Active: 2012-2013
Publications (10 Years): 0

Top Topics

Design Considerations

Power Dissipation

Top Venues

Publications

Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit. CoRR (2013)
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. CoRR (2013)
Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. ISED (2012)