A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme.
Dipankar SahaSubhramita BasakSagar MukherjeeChandan Kumar SarkarPublished in: CoRR (2013)
Keyphrases
- power consumption
- low power
- low voltage
- power management
- cmos technology
- power dissipation
- logic circuits
- high speed
- high power
- energy efficiency
- mixed signal
- power saving
- single chip
- low cost
- energy saving
- power reduction
- image sensor
- data center
- low power consumption
- nm technology
- digital signal processing
- data flow
- gate array