Manash Chanda

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 7

Top Topics

Mathematical Analysis

Ultra Low Power

Top Venues

Comput. Electr. Eng.

IET Circuits Devices Syst.

Microelectron. J.

IEEE Trans. Artif. Intell.

Publications

Adrija Mukherjee, Papiya Debnath, D. Nirmal, Manash Chanda
A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications. Microelectron. J. 133 (2023)
Tanushree Ganguli, Manash Chanda, Angsuman Sarkar
Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime. Comput. Electr. Eng. 100 (2022)
Gargi Jana, Dipanjan Sen, Papiya Debnath, Manash Chanda
Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor. Comput. Electr. Eng. 99 (2022)
Shreya Bhattacharyya, Souvik Majumder, Papiya Debnath, Manash Chanda
Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm. IEEE Trans. Artif. Intell. 2 (3) (2021)
Avtar Singh, Saurabh Chaudhury, Manash Chanda, Chandan Kumar Sarkar
Split gated silicon nanotube FET for bio-sensing applications. IET Circuits Devices Syst. 14 (8) (2020)
Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing. IET Circuits Devices Syst. 12 (4) (2018)
Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application. J. Low Power Electron. 13 (3) (2017)
Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Manash Chanda, Swapnadip De, Chandan Kumar Sarkar
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application. J. Circuits Syst. Comput. 24 (10) (2015)
Manash Chanda, Ananda Sankar Chakraborty, S. Nag, R. Modak
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application. VDAT (2014)