Jyotishman Saikia

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 11

Top Topics

Vowel Recognition

Structured Sparsity

Convolutional Neural Networks

Floating Point Arithmetic

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-Sun Seo, Mingoo Seok
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits 59 (6) (2024)
Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-Sun Seo, Mingoo Seok
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. IEEE J. Solid State Circuits 58 (5) (2023)
Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas K. Venkataramanaiah, Deliang Fan, Jae-Sun Seo
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro. ESSCIRC (2023)
Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-Sun Seo
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity. IEEE J. Solid State Circuits 58 (7) (2023)
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. CICC (2022)
Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification. ESSCIRC (2022)
Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. DATE (2021)
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. VLSI Circuits (2021)
Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM. ISLPED (2019)
Sandeep Mishra, Telajala Venkata Mahendra, Jyotishman Saikia, Anup Dandapat
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2018)
Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access. VLSI Design (2017)