A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
Bo ZhangJyotishman SaikiaJian MengDewei WangSoonwan KwonSungmeen MyungHyunsoo KimSang Joon KimJae-sun SeoMingoo SeokPublished in: CICC (2022)