Low-power content addressable memory design using two-layer P-N match-line control and sensing.
Sheikh Wasmir HussainTelajala Venkata MahendraSandeep MishraAnup DandapatPublished in: Integr. (2020)
Keyphrases
- low power
- single chip
- power consumption
- high speed
- low cost
- vlsi architecture
- low power consumption
- logic circuits
- gate array
- digital signal processing
- data acquisition
- power dissipation
- cmos technology
- image sensor
- design process
- power reduction
- sensor networks
- mixed signal
- nm technology
- signal processing
- ultra low power