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Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture.
Dong Xiang
Kaiwei Li
Hideo Fujiwara
Krishnaiyan Thulasiraman
Jiaguang Sun
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2007)
Keyphrases
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low power
power consumption
vlsi architecture
high speed
low cost
cmos technology
single chip
wireless transmission
vlsi circuits
mixed signal
high power
low power consumption
nm technology
image sensor
digital signal processing
gate array
logic circuits