Terumine Hayashi

Publication Activity (10 Years)

Years Active: 1986-2009
Publications (10 Years): 0

Publications

Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi
Obstacle to training SpikeProp networks - Cause of surges in training process -. IJCNN (2009)
Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
Shape of error surfaces in SpikeProp. IJCNN (2008)
Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi
Enhancing both generalization and fault tolerance of multilayer neural networks. IJCNN (2007)
Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita
Descriptive Answer Clustering System for Immediate Feedback. ICCE (2007)
Terumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing. ATS (2006)
Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. IJCNN (2006)
Tsuyoshi Shinogi, Hiroyuki Yamada, Terumine Hayashi, Shinji Tsuruoka, Tomohiro Yoshikawa
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture. Asian Test Symposium (2005)
Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
On Test Data Compression Using Selective Don't-Care Identification. J. Comput. Sci. Technol. 20 (2) (2005)
Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase
Test data compression technique using selective don't-care identification. ASP-DAC (2004)
Yusei Katsuda, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
Manipulation of hidden units activities for fault tolerant multi-layer neural networks. CIRA (2003)
Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka
Between-Core Vector Overlapping for Test Cost Reduction in Core Testing. Asian Test Symposium (2003)
Tsuyoshi Shinogi, Tomokazu Kanbayashi, Tomohiro Yoshikawa, Shinji Tsuruoka, Terumine Hayashi
Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems. Asian Test Symposium (2001)
Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi
An enhanced fault model for high defect coverage. Systems and Computers in Japan 32 (6) (2001)
Tsuyoshi Shinogi, Masahiro Ushio, Terumine Hayashi
Cyclic greedy generation method for limited number of IDDQ tests. Asian Test Symposium (2000)
Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita
Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. IJCNN (3) (2000)
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. ASP-DAC (1999)
Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits. Systems and Computers in Japan 30 (7) (1999)
Tsuyoshi Shinogi, Terumine Hayashi
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. Asian Test Symposium (1999)
Tsuyoshi Shinogi, Terumine Hayashi
A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Fault. VTS (1998)
Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
On a Logical Fault Model H1SGLF for Enhancing Defect Coverage. Asian Test Symposium (1998)
Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. Asian Test Symposium (1997)
Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita
An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. ASP-DAC (1997)
Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi
Sequential circuit test generation by real number simulation. Systems and Computers in Japan 24 (9) (1993)
Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
Sequential Test Generation Based on Real-Value Logic. ITC (1992)
Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. ICCAD (1991)
Hiroshi Date, Mitsuho Seki, Terumine Hayashi
LSI module placement methods using neural computation networks. IJCNN (1990)
Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama
Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC (1989)
Kuniaki Kishida, F. Shirotori, Y. Ikemoto, Shun Ishiyama, Terumine Hayashi
A delay test system for high speed logic LSI's. DAC (1986)