A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.
Tsuyoshi ShinogiTerumine HayashiPublished in: Asian Test Symposium (1999)
Keyphrases
- test set
- error rate
- logic circuits
- training set
- test data
- asynchronous circuits
- training data
- parallel processing
- high speed
- generation process
- test cases
- parallel implementation
- evaluation methodology
- information extraction
- active learning
- confidence intervals
- shared memory
- parallel computing
- feature vectors
- feature extraction
- analog vlsi