Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.
Tsuyoshi ShinogiTerumine HayashiKazuo TakiPublished in: Systems and Computers in Japan (1999)
Keyphrases
- test generation
- test cases
- circuit design
- built in self test
- mutation testing
- design automation
- high speed
- logic synthesis
- integrated circuit
- test sequences
- digital circuits
- delay insensitive
- logic circuits
- low power
- floating gate
- fault models
- static analysis
- fault model
- asynchronous circuits
- model based diagnosis
- symbolic execution
- cmos technology
- pattern matching
- high level
- fault diagnosis
- frequency domain
- databases
- image processing
- case study
- data sets