Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing.
Terumine HayashiNaotsugu IkedaTsuyoshi ShinogiHaruhiko TakaseHidehiko KitaPublished in: ATS (2006)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- test cases
- single chip
- vlsi circuits
- vlsi architecture
- cmos technology
- wireless transmission
- power reduction
- high power
- logic circuits
- digital signal processing
- low power consumption
- image compression
- compression algorithm
- transform domain
- mixed signal
- delay insensitive
- low complexity
- gate array