Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor.
Tadahiko NishimukaiHideo InayoshiKikuko TakagiKazuhiko IwasakiIkuya KawasakiM. HanawaTakeshi OkadaPublished in: ICCD (1988)
Keyphrases
- fpga device
- pipeline architecture
- hardware implementation
- efficient implementation
- memory subsystem
- prefetching
- query processing
- hit rate
- caching scheme
- cache management
- data access
- silicon on insulator
- memory hierarchy
- back end
- instruction set
- hash table
- access patterns
- processor core
- main memory
- input output
- data structure