Login / Signup

Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.

Yuki YamagataKenichi IchinoMasayuki AraiSatoshi FukumotoKazuhiko IwasakiMasayuki SatohHiroyuki ItabashiTakashi MuraiNobuyuki Otsuka
Published in: Asian Test Symposium (2003)
Keyphrases
  • hardware implementation
  • neural network
  • general purpose
  • power consumption
  • memory size
  • random access memory
  • low cost
  • memory management
  • signal processing