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Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits.
Kenichi Ichino
Ko-ichi Watanabe
Masayuki Arai
Satoshi Fukumoto
Kazuhiko Iwasaki
Published in:
IEICE Trans. Inf. Syst. (2004)
Keyphrases
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high speed
real time
parallel processing
neural network
low cost