Hiromichi Yamada

Publication Activity (10 Years)

Years Active: 1994-2009
Publications (10 Years): 0

Publications

Kenichiro Tanabe, Hiromichi Yamada
Representations of a fixed-point subalgebra of a class of lattice vertex operator algebras by an automorphism of order three. Eur. J. Comb. 30 (3) (2009)
Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka
A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery. DSN (2007)
Yasuo Sugure, Seiji Takeuchi, Yuichi Abe, Hiromichi Yamada, Kazuya Hirayanagi, Akihiko Tomita, Kesami Hagiwara, Takeshi Kataoka, Takanori Shimura
Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications. IEICE Trans. Electron. (6) (2006)
Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada
A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS (1997)
Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. IEEE J. Solid State Circuits 31 (7) (1996)
Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura
A 120-MHz BiCMOS superscalar RISC processor. IEEE J. Solid State Circuits 29 (4) (1994)
Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. IEEE J. Solid State Circuits 29 (3) (1994)