Modified Scan Flip-Flop for Low Power Testing.

Amit Mishra Nidhi Sinha Satdev Virendra Singh Sreejit Chakravarty Adit D. Singh

Published in: Asian Test Symposium (2010)

Keyphrases

low power
power dissipation
power consumption
low cost
cmos technology
high speed
flip flops
high power
single chip
digital signal processing
vlsi architecture
logic circuits
wireless transmission
gate array
low power consumption
vlsi circuits
low voltage
power reduction
multiple input
digital images
real time