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Improving CMOS open defect coverage using hazard activated tests.

Chao HanAdit D. Singh
Published in: VTS (2014)
Keyphrases
  • test suite
  • low cost
  • high speed
  • low power
  • defect detection
  • analog vlsi
  • data sets
  • neural network
  • artificial intelligence
  • test data
  • statistical tests
  • risk assessment
  • delay insensitive