On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time.

Jaidev Shenoy Kelly Ockunzzi Virendra Singh Kushal Kamal

Published in: VLSI Design (2019)

Keyphrases

high speed
neural network
artificial intelligence
low cost
real time
test cases
test data
significantly reduced
circuit design
diagnostic tests
database
data sets
decision making
high density
built in self test