Operand Isolation with Reduced Overhead for Low Power Datapath Design.

Lokesh Siddhu Amit Mishra Virendra Singh

Published in: VLSI Design (2014)

Keyphrases

low power
single chip
low power consumption
high speed
logic circuits
low cost
power consumption
vlsi architecture
digital signal processing
gate array
design process
power dissipation
cmos technology
nm technology
real time
image sensor
error correction
wireless transmission
ultra low power