Wenjing Rao

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 14

Top Topics

Bipartite Graph

Shannon Entropy

Processor Array

Top Venues

Publications

Vincent Dumoulin, Wenjing Rao, Natasha Devroye
On the Response Entropy of APUFs. CoRR (2024)
Zhenye Huang, Deyou Tang, Rong Zhao, Wenjing Rao
A scientific paper recommendation method using the time decay heterogeneous graph. Scientometrics 129 (3) (2024)
Vincent Dumoulin, Wenjing Rao, Natasha Devroye
Active learning for fast and slow modeling attacks on Arbiter PUFs. DSD (2023)
Vincent Dumoulin, Wenjing Rao, Natasha Devroye
Active learning for fast and slow modeling attacks on Arbiter PUFs. CoRR (2023)
Yeqi Wei, Wenjing Rao, Natasha Devroye
APUF Production Line Faults: Uniqueness and Testing. DATE (2023)
Yeqi Wei, Tim Fox, Vincent Dumoulin, Wenjing Rao, Natasha Devroye
APUF Faults: Impact, Testing, and Diagnosis. DATE (2022)
Jian Xu, Soumya Banerjee, Wenjing Rao
The existence of universally agreed fairest semi-matchings in any given bipartite graph. Theor. Comput. Sci. 818 (2020)
Soroush Khaleghi, Wenjing Rao
Repairability Enhancement of Scalable Systems with Locally Shared Spares. CoRR (2018)
Soroush Khaleghi, Wenjing Rao
Hardware Obfuscation Using Strong PUFs. ISVLSI (2018)
Soumya Banerjee, Wenjing Rao
A General Design Framework for Sparse Parallel Prefix Adders. ISVLSI (2017)
Jian Xu, Soumya Banerjee, Wenjing Rao
The Existence of Universally Agreed Fairest Semi-matchings in Any Given Bipartite Graph. COCOON (2017)
Soumya Banerjee, Wenjing Rao
A local reconfiguration based scalable fault tolerant many-processor array. ASP-DAC (2017)
Soumya Banerjee, Wenjing Rao
A general approach for highly defect tolerant Parallel Prefix Adder design. DATE (2016)
Soroush Khaleghi, Paolo Vinella, Soumya Banerjee, Wenjing Rao
An STT-MRAM based strong PUF. NANOARCH (2016)
Soumya Banerjee, Wenjing Rao
On the conditions of guaranteed k-fault tolerant systems supporting on-the-fly repairs. ICCD (2015)
Soroush Khaleghi, Kai Da Zhao, Wenjing Rao
IC Piracy prevention via Design Withholding and Entanglement. ASP-DAC (2015)
Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni
A standard cell approach for MagnetoElastic NML circuits. NANOARCH (2014)
Yehua Su, Wenjing Rao
An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Soumya Banerjee, Kai Da Zhao, Wenjing Rao, Milos Zefran
Decentralized self-balancing systems. VLSI-SoC (2013)
Yehua Su, Wenjing Rao
Defect-tolerant logic hardening for crossbar-based nanosystems. DATE (2013)
Soroush Khaleghi, Wenjing Rao
Spare sharing network enhancement for scalable systems. DFTS (2013)
Soroush Khaleghi, Wenjing Rao
Constructing spare sharing networks for reliability enhancement of scalable systems. SiPS (2013)
Wenjing Rao, Chengmo Yang, Ramesh Karri, Alex Orailoglu
Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge. Computer 44 (2) (2011)
Yehua Su, Wenjing Rao
Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously. ICCAD (2011)
Yehua Su, Wenjing Rao
On mismatch number distribution of nanocrossbar logic mapping. ICCD (2010)
Yehua Su, Wenjing Rao
Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis. DFT (2009)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Logic Mapping in Crossbar-Based Nanoarchitectures. IEEE Des. Test Comput. 26 (1) (2009)
Yehua Su, Wenjing Rao
Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures. NANOARCH (2009)
Wenjing Rao, Alex Orailoglu
Towards fault tolerant parallel prefix adders in nanoelectronic systems. DATE (2008)
Wenjing Rao, Alex Orailoglu, Keith Marzullo
Locality aware redundancy allocation in nanoelectronic systems. NANOARCH (2008)
Ilia Polian, Wenjing Rao
Selective Hardening of NanoPLA Circuits. DFT (2008)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Towards Nanoelectronics Processor Architectures. J. Electron. Test. 23 (2-3) (2007)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. DATE (2007)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays. DSN (2007)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Topology aware mapping of logic functions onto nanowire-based crossbar architectures. DAC (2006)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. VTS (2006)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics. ETS (2006)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Fault tolerant nanoelectronic processor architectures. ASP-DAC (2005)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. ICCD (2005)
Wenjing Rao, Alex Orailoglu, George Su
Frugal linear network-based test decompression for drastic test cost reductions. ICCAD (2004)
Wenjing Rao, Alex Orailoglu, Ramesh Karri
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. ITC (2004)
Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
Test application time and volume compression through seed overlapping. DAC (2003)
Wenjing Rao, Alex Orailoglu
Virtual Compression through Test Vector Stitching for Scan Based Designs. DATE (2003)