Giovanni Causapruno

Publication Activity (10 Years)

Years Active: 2014-2019
Publications (10 Years): 4

Top Topics

Physical Design

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Mario Cofano, Marco Vacca, Giulia Santoro, Giovanni Causapruno, Giovanna Turvani, Mariagrazia Graziano
Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms. Integr. 66 (2019)
Davide Giri, Giovanni Causapruno, Fabrizio Riente
Parallel and Serial Computation in Nanomagnet Logic: An Overview. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Giovanni Causapruno, Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
Reconfigurable Systolic Array: From Architecture to Physical Design for NML. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano
A Reconfigurable Array Architecture for NML. ISVLSI (2016)
Giovanni Causapruno, Gianvito Urgese, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Protein Alignment Systolic Array Throughput Optimization. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
Logic-in-Memory: A Nano Magnet Logic Implementation. ISVLSI (2015)
D. Pala, Giovanni Causapruno, Marco Vacca, Fabrizio Riente, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
Logic-in-Memory architecture made real. ISCAS (2015)
Giovanni Causapruno, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Interleaving in Systolic-Arrays: A Throughput Breakthrough. IEEE Trans. Computers 64 (7) (2015)
Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni
A standard cell approach for MagnetoElastic NML circuits. NANOARCH (2014)
Giovanni Causapruno, A. Audero, Sergio Tota, Massimo Ruo Roch
A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor. ApplePies (2014)
Guoping Xiao, Waqar Ahmad, Syed Azhar Ali Zaidi, Massimo Ruo Roch, Giovanni Causapruno
High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values. ApplePies (2014)