Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network.
Erik AnzaloneMaurizio CapraRiccardo PelosoMaurizio MartinaGuido MaseraPublished in: IIH-MSP (1) (2017)
Keyphrases
- low power
- sparse matrix
- low cost
- neural network
- single chip
- vlsi architecture
- digital signal processing
- high speed
- low power consumption
- power consumption
- signal processor
- field programmable gate array
- gate array
- image sensor
- hardware and software
- image processing
- real time
- power reduction
- pattern recognition
- embedded systems
- logic circuits
- parallel implementation
- cmos technology
- mixed signal
- hardware implementation
- rows and columns
- k means
- power dissipation
- random projections