FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories.
Syed Azhar Ali ZaidiMuhammad AwaisCarlo CondoMaurizio MartinaGuido MaseraPublished in: DASIP (2013)
Keyphrases
- ldpc codes
- field programmable gate array
- low power consumption
- decoding algorithm
- error correction
- embedded systems
- low density parity check
- message passing
- hardware implementation
- rate allocation
- flash memory
- low cost
- parallel computing
- low power
- channel coding
- image transmission
- associative memory
- high speed
- power consumption
- source coding
- error detection
- non binary
- forward error correction
- end to end
- belief propagation