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A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes.
Simone Zezza
Saeid Nooshabadi
Guido Masera
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2013)
Keyphrases
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vlsi implementation
vlsi architecture
filter bank
fir filters