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Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes.

Purushotham MurugappaVianney LapotreAmer BaghdadiMichel Jézéquel
Published in: RSP (2013)
Keyphrases
  • ldpc codes
  • low complexity
  • decoding algorithm
  • low density parity check
  • information theoretic
  • error correction
  • vlsi architecture