Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD.
Atif Raza JafriAmer BaghdadiMuhammad Najam-ul-IslamMichel JézéquelPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2017)
Keyphrases
- multi processor
- shared memory
- single processor
- packet switched
- multi core processors
- network on chip
- program execution
- level parallelism
- distributed processing
- management system
- multi core architecture
- heterogeneous systems
- master slave
- distributed memory
- distributed architecture
- loosely coupled
- parallel processing
- parallel architecture
- learning capabilities
- parallel programming
- routing algorithm
- processor array
- software architecture
- parallel processors
- parallel architectures
- processing elements
- data flow
- message passing
- real time