Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA.
Jérémy NadalAmer BaghdadiPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2021)
Keyphrases
- fpga implementation
- pipelined architecture
- parallel architecture
- hardware implementation
- parallel hardware
- hardware architecture
- real time
- parallel processing
- video decoder
- ldpc codes
- field programmable gate array
- processing elements
- systolic array
- hardware design
- low density parity check
- software implementation
- level parallelism
- low complexity
- distributed video coding
- turbo codes
- dedicated hardware
- fpga technology
- shared memory
- xilinx virtex
- low cost
- massively parallel
- hardware architectures
- distributed source coding
- reconfigurable hardware
- error correction
- parallel implementation
- parallel computing
- high speed
- vlsi architecture
- error concealment