Erik H. D'Hollander

Publication Activity (10 Years)

Years Active: 1983-2024
Publications (10 Years): 9

Top Topics

Matrix Multiplication

Field Programmable Gate Array

Hardware Design

Top Venues

Publications

Erik H. D'Hollander, Ewout Danneels, Karel-Brecht Decorte, Senne Loobuyck, Arne Vanheule, Ian Van Kets, Dirk Stroobandt
Exploring Large Language Models for Verilog Hardware Design Generation. IPDPS (Workshops) (2024)
Gerbrand De Laender, Erik H. D'Hollander
ZyPy: Intercepting NumPy operations for acceleration on FPGAs. HEART (2023)
Thomas Faict, Erik H. D'Hollander, Bart Goossens
Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. Algorithms 12 (8) (2019)
Erik H. D'Hollander
Empowering Parallel Computing with Field Programmable Gate Arrays. PARCO (2019)
Bruno da Silva, Jan G. Cornelis, An Braeken, Erik H. D'Hollander, Jan Lemeire, Abdellah Touhafi
Heterogeneous Cloud Computing: Design Methodology to Combine Hardware Accelerators. Cloudtech (2018)
Erik H. D'Hollander, Bruno Chevalier, Koen De Bosschere
Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA. FPT (2017)
Erik H. D'Hollander, Abdellah Touhafi
ParaFPGA 2017: Enlarging the Scope of Parallel Programming with FPGAs. PARCO (2017)
Erik H. D'Hollander
High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication. SIGARCH Comput. Archit. News 44 (4) (2016)
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi
ParaFPGA15: Exploring threads and trends in programmable hardware. PARCO (2015)
Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire
Comparing and combining GPU and FPGA accelerators in an image processing context. FPL (2013)
Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools. Int. J. Reconfigurable Comput. 2013 (2013)
Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire
Performance and toolchain of a combined GPU/FPGA desktop (abstract only). FPGA (2013)
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi
ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications. PARCO (2013)
Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi
Performance and Resource Modeling for FPGAs using High-Level Synthesis tools. PARCO (2013)
Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire
Performance and Programming Environment of a Combined GPU/FPGA Desktop. High Performance Computing Workshop (2) (2012)
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi
ParaFPGA 2011 - High Performance Computing with Multiple FPGAs: Design Methodology and Applications. PARCO (2011)
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi
ParaFPGA: Parallel Computing with Flexible Hardware. PARCO (2009)
Kristof Beyls, Erik H. D'Hollander
Refactoring for Data Locality. Computer 42 (2) (2009)
Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt
Efficient memory management for hardware accelerated Java Virtual Machines. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Erik H. D'Hollander, Kristof Beyls
High Performance Computing with FPGAs. High Performance Computing Workshop (2008)
Fabian Diet, Erik H. D'Hollander, Kristof Beyls, Harald Devos
Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. DELTA (2008)
Kristof Beyls, Erik H. D'Hollander
Refactoring Intermediately Executed Code to Reduce Cache Capacity Misses. J. Instr. Level Parallelism 10 (2008)
Erik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi
Parallel Computing with FPGAs - Concepts and Applications. PARCO (2007)
Harald Devos, Kristof Beyls, Mark Christiaens, Jan M. Van Campenhout, Erik H. D'Hollander, Dirk Stroobandt
Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations. Trans. High Perform. Embed. Archit. Compil. 1 (2007)
Kristof Beyls, Erik H. D'Hollander
Intermediately executed code is the key to find refactorings that improve temporal data locality. Conf. Computing Frontiers (2006)
Kristof Beyls, Erik H. D'Hollander
Discovery of Locality-Improving Refactorings by Reuse Path Analysis. HPCC (2006)
Kristof Beyls, Erik H. D'Hollander, Frederik Vandeputte
RDVIS: A Tool that Visualizes the Causes of Low Locality and Hints Program Optimizations. International Conference on Computational Science (2) (2005)
Kristof Beyls, Erik H. D'Hollander
Generating cache hints for improved program efficiency. J. Syst. Archit. 51 (4) (2005)
Yijun Yu, Jianguo Lu, John Mylopoulos, Weiwei Sun, Jing-Hao Xue, Erik H. D'Hollander
Making XML document markup international. Softw. Pract. Exp. 35 (1) (2005)
Yijun Yu, Kristof Beyls, Erik H. D'Hollander
Performance Visualizations using XML Representations. IV (2004)
Kristof Beyls, Erik H. D'Hollander
Platform-Independent Cache Optimization by Pinpointing Low-Locality Reuse. International Conference on Computational Science (2004)
Fubo Zhang, Erik H. D'Hollander
Using Hammock Graphs to Structure Programs. IEEE Trans. Software Eng. 30 (4) (2004)
Yijun Yu, Erik H. D'Hollander
Non-Uniform Dependences Partitioned by Recurrence Chains. ICPP (2004)
Kristof Beyls, Erik H. D'Hollander, Yijun Yu
Visualization Enables the Programmer to Reduce Cache Misses. IASTED PDCS (2002)
Kristof Beyls, Erik H. D'Hollander
Reuse Distance-Based Cache Hint Selection. Euro-Par (2002)
Yijun Yu, Kristof Beyls, Erik H. D'Hollander
Visualizing the Impact of the Cache on Program Execution. IV (2001)
Henk J. Sips, Ruud Sommerhalder, Erik H. D'Hollander
Linear systems and associated problems - introduction. Parallel Comput. 27 (7) (2001)
Yijun Yu, Erik H. D'Hollander
Loop Parallelization using the 3D Iteration Space Visualizer. J. Vis. Lang. Comput. 12 (2) (2001)
Kristof Beyls, Erik H. D'Hollander
Cache Remapping to Improve the Performance of Tiled Algorithms. Euro-Par (2000)
Yijun Yu, Erik H. D'Hollander
Partitioning Loops with Variable Dependence Distances. ICPP (2000)
Kristof Beyls, Erik H. D'Hollander
Compiler Generated Multithreading to Alleviate Memory Latency. J. Univers. Comput. Sci. 6 (10) (2000)
Kristof Beyls, Erik H. D'Hollander, Yijun Yu
JPT: A Java Parallelization Tool. PVM/MPI (1999)
Erik H. D'Hollander, Fubo Zhang, Qi Wang
The FORTRAN Parallel Transformer and its Programming. Inf. Sci. 106 (3-4) (1998)
Qi Wang, Yijun Yu, Erik H. D'Hollander
Visualizing the Iteration Space in PEFPT. HPCN Europe (1997)
Erik H. D'Hollander, Fubo Zhang
PVM Code Generator for the Fortran Parallel Transformer. PDPTA (1996)
Fubo Zhang, Erik H. D'Hollander
Extracting the Parallelism in Program with Unstructured Control Statements. ICPADS (1994)
Fubo Zhang, Erik H. D'Hollander
Enhancing Parallelism by Removing Cyclic Data Dependencies. PARLE (1994)
Fubo Zhang, Erik H. D'Hollander
Using Hammock Graphs to Eliminate Nonstructured Branch Statements. PARLE (1993)
Wim Van de Velde, Johan Opsommer, Erik H. D'Hollander
Performance Modeling of Microkernel Thread Schedulers for Shared Memory Multiprocessors. PARLE (1993)
Erik H. D'Hollander
Partitioning and Labeling of Loops by Unimodular Transformations. IEEE Trans. Parallel Distributed Syst. 3 (4) (1992)
Erik H. D'Hollander, Yves Devis
Directed Taskgraph Scheduling Using Simulated Annealing. ICPP (2) (1991)
Erik H. D'Hollander
Partitioning and Labeling of Index Sets in DO Loops with Constant Dependence Vectors. ICPP (2) (1989)
Erik H. D'Hollander, Johan Opsommer
Implementation of An Automatic Program Partitioner on a Homogeneous Multiprocessor. ICPP (1987)
Erik H. D'Hollander, H. Simoens
A Simulator of Homogeneous Multiprocessor Systems. ESC (1983)