Chia-Chen Chou

Publication Activity (10 Years)

Years Active: 2010-2018
Publications (10 Years): 6

Top Topics

Computational Power

Cache Conscious

Bandwidth Utilization

Top Venues

Publications

Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. ISCA (2018)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. MEMSYS (2017)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
CANDY: Enabling coherent DRAM caches for multi-node systems. MICRO (2016)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ISCA (2015)
Prashant J. Nair, Chia-Chen Chou, Bipin Rajendran, Moinuddin K. Qureshi
Reducing read latency of phase change memory via early read and Turbo Read. HPCA (2015)
Chia-Chen Chou, Prashant J. Nair, Moinuddin K. Qureshi
Reducing Refresh Power in Mobile Devices with Morphable ECC. DSN (2015)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. MICRO (2014)
Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
Refresh pausing in DRAM memory systems. ACM Trans. Archit. Code Optim. 11 (1) (2014)
Prashant J. Nair, Chia-Chen Chou, Moinuddin K. Qureshi
A case for Refresh Pausing in DRAM memory systems. HPCA (2013)
Yu-Hui Chen, Chia-Chen Chou, Hung-yi Lee, Lin-Shan Lee
An initial attempt to improve spoken term detection by learning optimal weights for different indexing features. ICASSP (2010)