Gary Lauterbach

Publication Activity (10 Years)

Years Active: 1994-2021
Publications (10 Years): 1

Top Topics

Semi Structured

Communication Infrastructure

Top Venues

Publications

Gary Lauterbach
The Path to Successful Wafer-Scale Integration: The Cerebras Story. IEEE Micro 41 (6) (2021)
Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. HPCA (2013)
Ashutosh Dhodapkar, Gary Lauterbach, Sean Lie, Dhiraj Mallick, Jim Bauman, Sundar Kanthadai, Toru Kuzuhara, Gene Shen, Min Xu, Chris Zhang
SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips. Hot Chips Symposium (2011)
Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication. Hot Interconnects (2005)
Ilya Sharapov, Gary Lauterbach, Stephen P. Crago
Robust Highly-Connected Direct Interconnection Network Topologies. PDPTA (2003)
Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You
A third-generation SPARC V9 64-b microprocessor. IEEE J. Solid State Circuits 35 (11) (2000)
Tim Horel, Gary Lauterbach
UltraSPARC-III: designing third-generation 64-bit performance. IEEE Micro 19 (3) (1999)
Gary Lauterbach
Vying for the Lead in High-Performance Processors (Interview). Computer 32 (6) (1999)
Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. IEEE J. Solid State Circuits 33 (11) (1998)
William L. Lynch, Gary Lauterbach, Joseph I. Chamdani
Low Load Latency Through Sum-Addressed Memory (SAM). ISCA (1998)
Gary Lauterbach
Accelerating Architectural Simulation by Parallel Execution of Trace Samples. HICSS (1) (1994)