64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.
Raymond A. HealdKen ShinVinita ReddyI-Feng KaoMasood KhanWilliam L. LynchGary LauterbachJoe PetolinoPublished in: IEEE J. Solid State Circuits (1998)
Keyphrases
- prefetching
- network simulator
- main memory
- data transfer
- wireless sensor networks
- cache conscious
- memory hierarchy
- query processing
- routing protocol
- data access
- higher throughput
- memory bandwidth
- memory subsystem
- caching scheme
- cache misses
- hit ratio
- virtual memory
- memory access
- response time
- web caching
- access latency
- garbage collection
- replacement policy
- computing power
- database systems